MetalStack white paperWP-01MetalStack Core32 / 28 nm

Full-chip EM, TM and IR-drop validation

AbstractRule-based electromigration checks assume a uniform die temperature and a fixed current limit per wire. Real power grids violate both assumptions. We ran MetalStack Core on six power grids extracted from Synopsys Fusion Compiler at 32/28 nm, solving electromigration, thermomigration and IR-drop as one coupled problem under measured and simulated thermal maps. Two designs degrade from a healthy day-one voltage drop to a failing one within a year, driven by a small minority of their nets. We also show that two thermal maps with identical average and peak temperature produce opposite verdicts on the same design, and that the sensitivity of lifetime to manufacturing spread varies by three orders of magnitude between designs — so neither can be covered by a fixed margin.

1 / THE PROBLEM

Why a single current limit is the wrong question

The conventional check asks whether any wire exceeds a current-density limit derived from Black’s equation at an assumed temperature. It is cheap, and it is wrong in both directions.

It is over-conservative on the wires that will never fail, and blind to the ones that will, because the limit cannot see where the heat sits relative to where the current flows. MetalStack solves the governing physics instead: current through the grid sets the Joule heating, the thermal map sets the migration rates, and the resulting voids change the resistance, which changes the current. The analysis is run forward through the design’s service life with that feedback closed rather than evaluated once at time zero.

2 / SIX DESIGNS

Six industrial-scale designs, start to finish

Real power grids pulled from Synopsys Fusion Compiler at 32/28 nm — not toy test cases.

What MetalStack Core found in each design, and how long the analysis took.
Design	Size	Voltage drop, new	Voltage drop, aged	Lifetime	Analysis time
AES engine	97 nets	6.1%	6.9%	passes	3.8 s
ARM pad ring	68 nets	0.3%	0.3%	passes	2.0 s
JPEG codec	178 nets	6.6%	6.8%	passes	12.9 s
Dual RAM	55 nets	0.1%	0.1%	passes	1.6 s
RISC-V core	186 nets	6.2%	29.6%	9.4 months	4.5 s
ARM logic core	208 nets	8.9%	22.2%	4.0 months	31.5 s

The RISC-V core looks healthy on day one. It starts at 6.2% voltage drop and degrades to 29.6%, and only 18 of its 186 nets are responsible. A handful of overloaded wires can take down a grid that passes every check you would run today. Note the runtime column too: the largest design finishes in half a minute, which is what makes this something you run on every iteration rather than once before tape-out.

RISC-V core finished physical layout — **The design under test.** A real RISC-V core, placed and routed.

Extracted VDD power grid structure — **Its power grid.** Pulled straight out of the layout, nothing hand-built.

3 / THERMAL SENSITIVITY

Average temperature hides the answer

Each design was run under seven thermal maps spanning a 60-degree range: a flat reference, three self-heating profiles and three measured-chip profiles.

RISC-V core under seven thermal maps: a flat reference, three self-heating profiles and three measured-chip profiles.
Heat pattern	Average	Hotspot	Nets at risk	Lifetime
Flat 353K	353K	353K	7	5.0 months
Self-heating, cool	321K	346K	14	11.5 months
Self-heating, typical	353K	387K	18	9.4 months
Self-heating, hot	374K	407K	18	5.5 months
Measured chip, cool	310K	337K	12	7.1 months
Measured chip, typical	353K	388K	16	passes
Measured chip, hot	373K	408K	16	passes

Rows three and six carry the same average temperature and the same peak temperature, and reach opposite verdicts. One fails in nine months. The other passes. The only difference is where the hotspot lands relative to the current paths — which is precisely what a scalar temperature assumption throws away.

ARM Cortex-A core under the same seven thermal maps.
Heat pattern	Average	Hotspot	Nets at risk	Lifetime
Flat 353K	353K	353K	207	4.0 months
Self-heating, cool	320K	353K	206	4.0 months
Self-heating, typical	353K	385K	206	4.0 months
Self-heating, hot	373K	406K	206	4.0 months
Measured chip, cool	310K	342K	206	3.8 months
Measured chip, typical	353K	385K	206	3.8 months
Measured chip, hot	373K	406K	206	3.8 months

This design carries so much current that almost every net is at risk however it is cooled. Lifetime barely moves across the full 60-degree range. Cooling will not save it; the grid needs redesigning, and MetalStack says so before tape-out rather than after.

Input spatial temperature map for the RISC-V core — **Where the heat is.** A hotspot in the lower left, at 353K average.

3D coupled EM and TM stress map with nucleation sites — **Where the damage forms.** 18 nets at risk, with the failure points marked.

4 / WHAT FAILURE LOOKS LIKE

See exactly where it breaks

Real MetalStack output on the two failing grids above — not a diagram of what the tool could show you.

3D IR-drop map for the RISC-V core after aging — **What it costs you.** The same grid nine months in, past its voltage limit.

Steady-state stress map without nucleation — **Your weakest links.** The wires under the most strain, ranked.

ARM Cortex-A core stress map — **A grid in trouble.** 206 nets damaged, concentrated through the centre.

ARM Cortex-A core IR-drop map — **Failing at four months.** Voltage drop at more than double its budget.

5 / MANUFACTURING SPREAD

How far lifetime moves when the silicon does

100 runs per design with realistic material variation, carried through the coupled analysis rather than applied as a margin afterwards.

±16%Lifetime spread, RISC-V core

±0.006%Lifetime spread, ARM logic core

7–15Months the RISC-V core’s lifetime can land between

Three orders of magnitude apart, on the same analysis. The RISC-V core’s lifetime swings with how the silicon comes out; the ARM core lands in the same place every time. A single fixed margin would leave one over-designed and the other exposed, which is why the spread has to be measured per design rather than assumed.

Monte Carlo time-to-failure histogram for the RISC-V core — **Lifetime, with odds.** 100 runs showing the real spread rather than one number.

6 / EXACT ACCELERATION

Acceleration that does not change the answer

The numerical engine has its own acceleration, separate from the AI engine. It returns identical results — the speed is free.

Speedup from the numerical engine’s built-in acceleration, per design. Lifetime and IR-drop results are identical to the unaccelerated solve.
Design	Speedup
Dual RAM	1.50×
ARM logic core	1.29×
JPEG codec	1.26×
AES engine	1.21×
RISC-V core	1.21×
ARM pad ring	1.18×

Acceleration that changes your answer is not worth having. These runs return identical lifetime and IR-drop numbers to the unaccelerated solve. For the much larger speedups available when an approximation is acceptable, see WP-02.

7 / SCOPE

What this study does and does not establish

Study scope: six power grids extracted from Synopsys Fusion Compiler at 32/28 nm, analysed with MetalStack Core under seven thermal maps each, with 100-run Monte Carlo sampling on two of them. Runtimes are hardware-dependent and measured on a single workstation. These results characterise the designs listed above; they are not accuracy or lifetime guarantees for an arbitrary power grid. All figures on this page were generated by MetalStack on those grids.

From evidence to your design

Run this on a grid you actually ship.

Bring your power grid, your thermal map and the lifetime target you have to hit. We will walk you through the same analysis end to end, including the parts that look bad.

Request a demo