Inspect buried structures
Cross-sections and X-ray views relate temperature to die stacks, TSVs, microbumps and package connections. Contact temperatures reflect the thermal model's resolution and material assumptions.
1 / THE MODELED PACKAGE
Nonuniform power maps reveal local activity rather than treating every die as an identical uniform heater.
2 / TWO WORKLOADS
Two 950 W scenarios emphasize different parts of the assembly: compute in the GPU-intensive case and memory in the memory-intensive case. The thermal constraint moves from the compute chiplets toward memory as the power allocation shifts.
3 / RESOLUTION COMPARISON
The same numerical model was evaluated at both spatial sampling settings, retaining identical solver settings, power budgets and cooling conditions. The coarser X-Y grid contains 25 times fewer sample cells.
| Workload | Peak change | Worst sampled-field difference | Normalized difference* |
|---|---|---|---|
| GPU intensive | 0.0234 K | 0.0382 K | 0.0443% |
| Memory intensive | 0.0054 K | 0.0441 K | 0.0512% |
*Maximum absolute difference at compared sample locations, divided by the 50 µm result's peak temperature rise above 25 °C ambient. This is not pointwise percentage error or error relative to measured silicon.
In this study, the coarser model preserves the main thermal patterns and the package peak. That supports a workflow in which broad screening comes first, followed by higher-resolution investigation of selected hotspots and interfaces. It does not establish that every design can use the same coarse spacing.
4 / RESULT VIEWS
A temperature field becomes more useful when it stays attached to the structure that produced it.
Move between package-level maps, layer inspection and cross-sections to understand where heat is generated, how it spreads, and which structures limit thermal margin. Three-dimensional views expose relationships that a top-only heatmap can hide: the two workloads reach almost the same package peak, 111.25 °C and 111.17 °C, but in different silicon.
Z is exaggerated about 25× so the thin dies and bond layers stay visible; the compute stacks are not recessed in the real package, they are simply shorter than the HBM towers before the carrier is added. Contact outlines are subsampled for display.
Both views are the 50 µm runs behind section 3, on independent colour scales in kelvin. Height is exaggerated about 25× so the thin layers remain visible.
True X-Z section at y = 24 mm, through HBM stack H3 and the compute quads. Z is stretched about 23× against X; C4, µbump, TCB and TSV cut outlines are marked.
Cross-sections and X-ray views relate temperature to die stacks, TSVs, microbumps and package connections. Contact temperatures reflect the thermal model's resolution and material assumptions.
Use maps, exported figures and component-level results in design reviews. Keep geometry, workload and cooling context with the thermal conclusion.
5 / SCOPE & INTERPRETATION
Both runs use ThermStack's fast numerical solver, not a coarse-versus-fine FEM study. Only spatial sampling changes; the solver's representation is held fixed. The comparison uses linear interpolation of the finer result at coarse cell centers, considering finite occupied overlaps. Z sampling is unchanged.
The result demonstrates sampling consistency for these two assumed workloads, not independent FEM validation, proven 50 µm resolving power, or a guaranteed error bound. Thin features and sharply localized sources require their own refinement checks. The AMD reference is qualitative: this study is not endorsed by AMD and is not a measurement of an AMD product.
Source context: AMD Instinct MI350 Series GPUs, ISSCC 2026, session 2.1, and the supplied GPU-intensive / memory-intensive workload illustration. Numerical values are from the ThermStack AMD resolution study.
From evidence to your design
Start with your package, expected workloads and thermal margin. We will discuss input compatibility, the analysis path and the evidence needed for your decision.