ThermStack white paperWP-102October 2026

AMD-inspired accelerator study: workloads, resolution and result views

AbstractEight compute chiplets, two I/O dies and eight 12-high HBM stacks create a demanding test of package-level thermal analysis. This paper studies an AMD MI350-inspired assembly under two 950 W workloads — GPU-intensive and memory-intensive — and compares the same numerical model at 250 µm and 50 µm spatial sampling. In this study the coarser grid, with 25× fewer X-Y sample cells, preserves the package peak to within 0.024 K and the sampled field to within 0.06% of the fine result's peak temperature rise. Interactive 2D/3D result views on the modeled structure are included.

1 / THE MODELED PACKAGE

An MI350-inspired compute + memory assembly

Nonuniform power maps reveal local activity rather than treating every die as an identical uniform heater.

Modeled assembly, reconstructed for this study from public architecture context. Geometry, materials, activity maps and cooling include modeling assumptions.

2 / TWO WORKLOADS

Different workloads move the thermal constraint

Two 950 W scenarios emphasize different parts of the assembly: compute in the GPU-intensive case and memory in the memory-intensive case. The thermal constraint moves from the compute chiplets toward memory as the power allocation shifts.

Power allocation and resulting temperature maps for the two workloads. Illustrative AMD-inspired model; not measured AMD silicon or an AMD-endorsed result.

3 / RESOLUTION COMPARISON

250 µm versus 50 µm sampling

The same numerical model was evaluated at both spatial sampling settings, retaining identical solver settings, power budgets and cooling conditions. The coarser X-Y grid contains 25 times fewer sample cells.

<0.06%Worst sampled-field difference relative to the fine result's peak rise
<0.024 KLargest change in package peak temperature across the two workloads
25×Fewer X-Y samples; not a claimed 25× solver speedup
Measured differences between the 250 µm and 50 µm runs
WorkloadPeak changeWorst sampled-field differenceNormalized difference*
GPU intensive0.0234 K0.0382 K0.0443%
Memory intensive0.0054 K0.0441 K0.0512%

*Maximum absolute difference at compared sample locations, divided by the 50 µm result's peak temperature rise above 25 °C ambient. This is not pointwise percentage error or error relative to measured silicon.

Top-surface thermal patterns at coarse and fine sampling. The tabulated worst differences compare the occupied volume, not just these top surfaces.

Why this matters for exploration

In this study, the coarser model preserves the main thermal patterns and the package peak. That supports a workflow in which broad screening comes first, followed by higher-resolution investigation of selected hotspots and interfaces. It does not establish that every design can use the same coarse spacing.

4 / RESULT VIEWS

See temperature in context

A temperature field becomes more useful when it stays attached to the structure that produced it.

Move between package-level maps, layer inspection and cross-sections to understand where heat is generated, how it spreads, and which structures limit thermal margin. Three-dimensional views expose relationships that a top-only heatmap can hide: the two workloads reach almost the same package peak, 111.25 °C and 111.17 °C, but in different silicon.

AMD study / exported result views (50 µm runs)
Cutaway. Carrier silicon and filler hidden, so every chiplet is visible: eight XCDs (X1–X8) in two quads on IOD 1 and IOD 2, ringed by eight 12-high HBM stacks (H1–H8). Same instances, in the same places, as the floorplan in section 1.
As assembled. The same model with carrier and filler restored. The carrier caps the compute stacks level with the HBM tops, giving the planar surface that the 10,000 W/m²K top boundary is applied to. Both solves use this structure.

Z is exaggerated about 25× so the thin dies and bond layers stay visible; the compute stacks are not recessed in the real package, they are simply shorter than the HBM towers before the carrier is added. Contact outlines are subsampled for display.

Inspect buried structures

Cross-sections and X-ray views relate temperature to die stacks, TSVs, microbumps and package connections. Contact temperatures reflect the thermal model's resolution and material assumptions.

Share the engineering picture

Use maps, exported figures and component-level results in design reviews. Keep geometry, workload and cooling context with the thermal conclusion.

5 / SCOPE & INTERPRETATION

What this study does and does not establish

Both runs use ThermStack's fast numerical solver, not a coarse-versus-fine FEM study. Only spatial sampling changes; the solver's representation is held fixed. The comparison uses linear interpolation of the finer result at coarse cell centers, considering finite occupied overlaps. Z sampling is unchanged.

The result demonstrates sampling consistency for these two assumed workloads, not independent FEM validation, proven 50 µm resolving power, or a guaranteed error bound. Thin features and sharply localized sources require their own refinement checks. The AMD reference is qualitative: this study is not endorsed by AMD and is not a measurement of an AMD product.

Source context: AMD Instinct MI350 Series GPUs, ISSCC 2026, session 2.1, and the supplied GPU-intensive / memory-intensive workload illustration. Numerical values are from the ThermStack AMD resolution study.

From evidence to your design

Define the study that answers your question.

Start with your package, expected workloads and thermal margin. We will discuss input compatibility, the analysis path and the evidence needed for your decision.

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