Full-chip power integrity for million-node designs
From power-grid netlist to transient IR-drop. Run the full time-domain analysis in a fraction of a direct solve, and see where on the die the margin is actually lost.
Reconstructed from the benchmark netlist: the 15-layer metal mesh and the rail-aware drop field it produces.
Standard power-grid netlists with switching current sources; full voltage history at every probe node.
Advanced Krylov reduction for speed, standard Krylov for machine precision — same input, same flow.
Die-level structure, in-plane IR drop and 3D drop surfaces reconstructed straight from the netlist.
Capabilities
Dynamic IR-drop is decided by the full time-domain response of a mesh with millions of nodes and thousands of time steps. GridStack replaces the repeated full-grid solve with a compact reduced-order model, so the analysis can run every iteration instead of once at the end.
01 / TRANSIENT ANALYSIS
Drive the grid with arbitrary switching-current waveforms and read the complete voltage history at every probe node — droop, dynamic IR-drop and settling, across thousands of time points.
Transient method02 / SPEED WITHOUT COMPROMISE
An order-10 rational Krylov model stands in for the million-node mesh over the transient window. The waveforms track the direct solve to essentially machine-grade accuracy, at a fraction of the CPU time.
Validation results03 / VISUAL INSIGHT
Die-level metal structure, rail-aware IR drop and VSS bounce in plane, and the same field lifted into 3D — reconstructed from the netlist itself, with no external layout database required.
Full-chip views04 / DESIGN EXPLORATION
The reduced model is built once and is independent of the stimulus, so each new current scenario costs only the reduced march. Power profiles, decap placements and floorplan variants become practical to compare.
Why sweeps are cheap05 / PARALLEL SCALE-OUT
Partition the grid into balanced subdomains, solve each independently across multi-core CPUs and GPUs, and stitch the solution together at the shared boundary nodes — the full-grid answer, computed a piece at a time.
Detailed in WP-03, in preparation.
06 / FLOW INTEGRATION
A CLI-first interface and structured, machine-readable results let an autonomous flow invoke transient analysis, read back waveforms and IR-drop margins, and steer the next floorplan or decap decision without a GUI in the loop.
Detailed in WP-04, in preparation.
From netlist to decision
Keep the netlist, the stimulus and the resulting waveforms together. The same physical context carries from a first screening run through to the full-chip map used in a design review.
The power-grid netlist as the solver reads it, with its conductance and capacitance matrices and switching sources.
Pick the point on the speed–accuracy trade that the study needs; both modes run on the same input.
Use waveforms and die-level maps to decide what to change and where to look more closely.
White papers
This page stays short on purpose. Methods, benchmarks, figures, tables and their scope notes live in a growing series of white papers — each a self-contained document you can read, share and cite in a design review.
GS-WP-01 / METHOD & VALIDATION
The reduced-order method behind GridStack and its full validation against a direct back-Euler transient solve on the IBM power-grid benchmarks, from 54K to 1.04M nodes: CPU time, speedup and normalized waveform error for both solver modes.
Read GS-WP-01GS-WP-02 / VISUALIZATION
Reconstructing die-level metal structure and rail-aware IR drop / VSS bounce straight from the SPICE geometry — in plane and in 3D — for an 8-layer and a 15-layer IBM grid at the full-node back-Euler snapshot.
Read GS-WP-02GS-WP-03 / SIGN-OFF CORRELATION
Static and dynamic IR drop on two signed-off Fusion Compiler designs, a RISC core and a 242K-node LPU accelerator, compared cell by cell with in-design RedHawk-SC: worst-case drop within 0.6–1.6%, 3.8–11× faster dynamic and 23–27× faster static.
Read GS-WP-03GS-WP-04 / IN PREPARATION
Partitioning the grid into balanced subdomains, solving them independently across cores and GPUs, and stitching at the shared boundary nodes — with parallel-efficiency and scaling measurements.
In preparation.
GS-WP-05 / IN PREPARATION
The CLI and structured data interface, and how an autonomous agent closes the loop between transient IR-drop results and the next floorplan, decap or power-budget decision. Ask to be notified when a new paper is published.
Get notifiedStart with your grid
Discuss your power-grid size, stimulus and accuracy targets with the GridStack team, and see the flow run on a design of your own.