ChipletTherm — Fast 3D Chiplet Thermal Analysis (Static & Transient)

The bottleneck

3D integration broke the old thermal flow

Vertical stacking of dies, interposers, and memory turns thermal behavior into a first-order design constraint — and with accelerators now pushing 700–1200 W, the tools accurate enough to trust are far too slow to keep in the loop.

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Hotspots hide in the stack

Heterogeneous 2.5D/3D stacks raise thermal resistance and trap heat between layers. Logic chiplets next to stacked HBM create localized hotspots — and peak junction temperature decides whether a design ships.

🐌

3D FEM is too slow to iterate

A full 3D finite-element solve discretizes the whole volume into millions of unknowns. That's fine for one sign-off, but impossible for the thousands of evaluations a design-space search — or a runtime control loop — demands.

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Thermal must be in the loop

Floorplanning, power delivery, packaging co-design, and runtime management all need temperature feedback per iteration. Without a fast, accurate model, thermal gets checked last — when it's most expensive to fix.

The ChipletTherm flow — power in, thermal map out

Inputs

⚡Thermal power mapsfrom your EDA flow

🧱Chiplet structure2.5D / 3D stack-up & layers

🧪Material propertiesper-layer conductivity & more

→

ChipletTherm · pick the solver

3D · ChipletTherm (TASTA)thickness-resolved — most accurate

2D · ChipletTherm-2D (TASTA-2D)layer-averaged — fastest

→

Thermal map

2D heat mapper-layer & hotspot view

3D temperature fieldresolved through the stack

What it does

One engine, the whole thermal picture

ChipletTherm pairs a fast spectral solver with a full 3D-FEM reference, covering both steady-state sign-off and time-dependent response on the very same chiplet model.

STATIC

🗺️ Resolved 3D heat maps

Full-chip, full-stack temperature fields for 2.5D and 3D assemblies — every die, layer, and interposer resolved through-thickness in 3D from a single power and floorplan description.

TRANSIENT

📈 Time-domain response

Drive the model with arbitrary power waveforms and get the full temperature history at every node — thermal transients, throttling, and workload bursts, step by step.

SPEED

⚡ Real-time fast

Steady-state solves land in ~0.02 s and transients in well under a second — up to 1410× faster than 3D FEM (static) and a mean 1036× (transient). Fast enough for ~50 Hz runtime thermal management.

ACCURACY

🎯 Best-in-class fidelity

ChipletTherm reaches 0.21 K mean RMSE against a consistent-mass 3D-FEM reference — more accurate than the SOV and GIT semi-analytical baselines — across 30 cases including measured Snapdragon and Coral-TPU power maps.

SCOPE

🧱 Real chiplet stacks

Validated to 11 layers — 2.5D interposers, 3D logic stacks, HBM, CPU and RF packages — with per-layer anisotropic materials, interface thermal resistance, heat capacity, and convective surface cooling.

EXPLORE

🔭 Batched & scriptable

Lateral frequency modes solve independently, so workloads batch naturally across multi-core CPUs and GPUs — built to evaluate thousands of candidate designs or stream live temperature estimates.

Workflow · ChipletTherm integration

Built for agentic EDA flows

ChipletTherm is designed to plug directly into agentic EDA workflows. A first-class CLI and structured data interface let autonomous design agents invoke fast static or transient thermal analysis, consume machine-readable temperature maps and margins, and feed those results back into floorplanning, stack planning, power budgeting, and optimization loops.

Fully agentic-flow aware — built to be driven by autonomous EDA agents, and to plug into any agentic flow.
First-class CLI — every analysis is scriptable from the command line; nothing in the loop needs a GUI.
Structured data interface — machine-readable inputs, temperature fields, hotspot locations, and thermal margins for closed-loop automation.
Thermal-aware design iteration — agents can sweep floorplans, stack-ups, power maps, and cooling assumptions, then use ChipletTherm results to steer the next candidate.

agentic-flow aware CLI-first structured data interface thermal maps closed-loop optimization

Closed-loop automation

◆ Agentic EDA flow

An autonomous agent drives floorplan, power, and routing decisions.

↓ invokes ChipletTherm — CLI + structured data interface

▣ ChipletTherm thermal analysis

Static and transient solvers run headless, producing temperature maps and thermal margins directly for automation.

↓ returns structured, machine-readable results

↻ Fed back to the agent

Hotspots, gradients, and thermal margins steer the next floorplan, stack, or power-budget iteration automatically.

Thermal analysis becomes a callable step inside your agentic EDA flow, not a hand-run GUI task.

Under the hood

Spectral in the plane, thickness-aware through the stack

The speed comes from analyzing the chip in a form where the physics nearly separates. ChipletTherm breaks the in-plane temperature field into independent spectral (cosine) modes, resolves each one down through the layer stack, and reassembles the full 3D map. It ships in two solver modes that span the speed–accuracy tradeoff: ChipletTherm (TASTA), the thickness-resolved, most-accurate solver, and ChipletTherm-2D (TASTA-2D), the fast, layer-averaged one. TASTA / TASTA-2D are the names used in our paper and figures.

Spectral decomposition

The in-plane temperature pattern is broken into a set of simple, wave-like spatial modes using a spectral transform. This is the key move: it turns one large, tightly-coupled 3D problem into many small, completely independent ones.

Layer-aware vertical model

Each mode is resolved straight down through the physical stack — every die, bonding layer, and interposer — using their real per-layer materials, directional conductivity, and interface resistances.

Massively parallel solve

Because the modes are completely independent, they are all solved at once — directly, in a single pass — which is exactly what makes the analysis fast and a natural fit for multi-core CPU and GPU hardware.

Reassemble the temperature map

The solved modes recombine into the complete temperature field — the steady-state map directly, or advanced step-by-step through time for transient analysis.

ChipletTherm-2D (TASTA-2D)

fastest

Layer-averaged: one in-plane field per physical layer, coupled by effective interface resistances. The lowest-cost thermal estimate.

0.016 s
per case0.44 K
avg RMSE

ChipletTherm (TASTA)

most accurate

Thickness-resolved: a layer-aware 1D finite-difference scheme recovers the full 3D field. Best accuracy of every method tested.

0.020 s
per case0.21 K
avg RMSE

Why it's fast

Full 3D FEM grinds through one giant system with millions of unknowns. The spectral approach instead splits the chip into hundreds of simple, independent thermal patterns — each tiny and solvable on its own, all at the same time. Replacing one enormous problem with hundreds of trivial ones, solved in parallel, is where the 100–1000× speedup comes from — with no loss of accuracy versus FEM.

spectral method fully decoupled modes solved in parallel CPU & GPU ready anisotropic materials interface resistance FEM-grade accuracy

A full 3D finite-element solver ships alongside as the ground-truth reference, and every ChipletTherm result is validated against it.

Validation

Measured against full 3D FEM

Every number below is benchmarked against a consistent-mass 3D-FEM reference: 18 static cases (6 real designs × 3 power inputs, up to 11 layers) and 12 transient cases (100 time steps each), spanning CPU, GPU, TPU, HBM, and RF power profiles.

Static — steady-state sign-off

Accuracy & speed vs. baselines

Avg over 18 cases, RMSE vs FEM-3D reference

most accurate

Method	Avg RMSE	Runtime
FEM-3D reference	—	12.7 s
SOV baseline	0.225 K	0.047 s
GIT baseline	0.219 K	0.348 s
ChipletTherm-2D TASTA-2D · fastest	0.444 K	0.016 s
ChipletTherm TASTA · most accurate	0.214 K	0.020 s

ChipletTherm (TASTA) is more accurate than every baseline while running 2.42× / 21.4× / 637× faster than SOV / GIT / FEM-3D. ChipletTherm-2D (TASTA-2D) is the single fastest method of all, at 0.016 s/case.

ChipletTherm speedup over 3D FEM

By benchmark design (#layers)

avg 637×

11-layer 3D IC

1410×

2.5D chiplet

872×

HBM3 stack

586×

5 nm CPU

563×

GaAs RFPA

304×

3-layer stack

89×

FEM-3D takes 1–34 s per design; ChipletTherm returns all of them in 0.014–0.027 s — at 0.094–1.35 K RMSE.

ChipletTherm-2D vs FEM-3D temperature fields across all six benchmark designs, with error maps — **ChipletTherm-2D (TASTA-2D) vs. FEM-3D across all six benchmark designs** (Google Coral M.2 TPU power input). Top row: ChipletTherm-2D. Middle: the 3D-FEM reference. Bottom: the error field — near-zero everywhere. The figure labels this solver “Fast2D-FD” (TASTA-2D) — it is ChipletTherm-2D.

ChipletTherm-2D 3D temperature field, HBM3 stack — **ChipletTherm-2D (TASTA-2D)** — HBM3 stack, Qualcomm Snapdragon 680 power input. Figure label: “Fast2D-FD”.

FEM-3D reference 3D temperature field, HBM3 stack — **FEM-3D reference** — same case. Visually indistinguishable, at ≈0.04 K RMSE.

Transient — time-domain response

Solve-time speedup

ChipletTherm-2D vs FEM-3D, per design family

mean 1036×

Chiplet 2.5D

≈1585×

CPU 5nm

≈1212×

3-layer 3D

≈252×

Peak observed speedup 1875× (Chiplet 2.5D, Edge-TPU trace). ChipletTherm-2D solves in 0.12–0.45 s across 100 time steps; the FEM-3D reference takes 30–733 s.

Accuracy

Temperature error vs FEM-3D reference

0.18% mean

Design family	RMSE	Mean error
Chiplet 2.5D	0.72 K	0.12%
CPU 5nm	1.42 K	0.24%
3-layer 3D	1.52 K	0.23%
All 12 cases	1.22 K	0.18%

Best case 0.57 K RMSE · worst case 2.09 K · peak temperatures matched within tenths of a kelvin across the 308–510 K range spanned by the benchmark.

Transient response — the two solvers overlap

Representative junction-temperature rise under a stepped power waveform (schematic of the <1.2 K agreement)

FEM-3D reference ChipletTherm-2D (TASTA-2D) Curves overlap to within the benchmark RMSE; shape is illustrative, errors are measured.

3D transient — Chiplet 2.5D · Intel Core i5 (FLAC)

Power inputs → ChipletTherm (TASTA) 3D temperature field, over time

3D · animated

assets/figs/videos/fast2d_fd_chiplet_i5_flac_volume3d.mp4 — copy videos to assets/figs/videos/ (see README)

ChipletTherm (TASTA) · output3D temperature field. The resolved, through-stack thermal response evolving over time.

assets/figs/videos/CPU_i5_flac_power_density_3d.mp4 — copy videos to assets/figs/videos/ (see README)

Input · 3DPower density, 3D. The time-varying volumetric power that drives the analysis.

assets/figs/videos/CPU_i5_flac_power_density.mp4 — copy videos to assets/figs/videos/ (see README)

Input · 2DPower density, 2D map. The per-layer input power over time.

A Chiplet 2.5D design driven by a measured Intel Core i5 (FLAC workload) power trace. As the workload's power density evolves in time (center & right), ChipletTherm resolves the full 3D transient temperature field (left) — the hotspot forming and spreading through the stack, step by step. From results_chiplet_i5_flac.

3D transient — Chiplet 2.5D · Intel Core i7 (GIMP)

Power inputs → ChipletTherm (TASTA) 3D temperature field, over time

3D · animated

assets/figs/videos/fast2d_fd_chiplet_i7_gimp_volume3d.mp4 — copy videos to assets/figs/videos/ (see README)

ChipletTherm (TASTA) · output3D temperature field. The resolved, through-stack thermal response evolving over time.

assets/figs/videos/CPU_i7_gimp_power_density_3d.mp4 — copy videos to assets/figs/videos/ (see README)

Input · 3DPower density, 3D. The time-varying volumetric power that drives the analysis.

assets/figs/videos/CPU_i7_gimp_power_density.mp4 — copy videos to assets/figs/videos/ (see README)

Input · 2DPower density, 2D map. The per-layer input power over time.

The same Chiplet 2.5D design under a measured Intel Core i7 (GIMP workload) power trace. The image-processing load spreads power differently than the i5/FLAC run above — ChipletTherm resolves the matching 3D transient temperature field (left) straight from it. From results_chiplet_i7_gimp.

Thermal sign-off for 3D chiplet designs, up to 1400× faster.

3D integration broke the old thermal flow

Hotspots hide in the stack

3D FEM is too slow to iterate

Thermal must be in the loop

One engine, the whole thermal picture

🗺️ Resolved 3D heat maps

📈 Time-domain response

⚡ Real-time fast

🎯 Best-in-class fidelity

🧱 Real chiplet stacks

🔭 Batched & scriptable

Built for agentic EDA flows

Spectral in the plane, thickness-aware through the stack

Spectral decomposition

Layer-aware vertical model

Massively parallel solve

Reassemble the temperature map

Measured against full 3D FEM

Accuracy & speed vs. baselines

ChipletTherm speedup over 3D FEM

Solve-time speedup

Accuracy

Transient response — the two solvers overlap

3D transient — Chiplet 2.5D · Intel Core i5 (FLAC)

3D transient — Chiplet 2.5D · Intel Core i7 (GIMP)

Put thermal back in the loop.